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Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

Author(s):

A. Suresh Babu* and B. Anand   Pages 1 - 8 ( 8 )

Abstract:


A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Keywords:

LFSR, Wireless Communication System, Parallel Architectures, Encryption-Decryption, Security in Wireless Communication

Affiliation:

Department of ECE, Hindusthan College of Engineering and Technology, Coimbatore, Department of EEE, Hindusthan College of Engineering and Technology, Coimbatore



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